module alu_hier(A, B, Op, Out, Ofl, Z);

   input [15:0] A;
   input [15:0] B;
   input [3:0] Op;
   output [15:0] Out;
   output   Ofl;
   output Z;

   wire clk;
   wire rst;
   wire err;

   assign err = 1'b0;
 
   clkrst c0(
             // Outputs
             .clk                       (clk),
             .rst                       (rst),
             // Inputs
             .err                       (err)
            );

    alu a0(
            .op1(A),
            .op2(B),
            .aluctr(Op[3:0]),
            .out(Out),
            .carry_out(Ofl),
            .zero(Z)
         ); 
endmodule // alu_hier
